1. Field of the Invention
The present invention relates generally to data transmission apparatuses, and more particularly, to data transmission apparatuses for controlling packet flow of a data transmission path and a method of operating such apparatuses.
2. Description of the Background Art
Such a data processor as a FIFO (First-In.First-Out) memory or a data driven type information processor employs a data transmission apparatus using an asynchronous handshaking circuit. Such a data transmission apparatus includes a plurality of data transmission paths connected to each other to send and receive a transmission signal and a transmission acknowledging signal for autonomous data transfer.
FIG. 14 shows one example of a conventional data transmission path. A data transmission path 10a includes a transfer control circuit 11a and a data hold circuit 12a. The data hold circuit 12a holds input data DI and outputs the same as output data DO in response to a fall of a transmission signal C2 applied from the transfer control circuit 11a.
FIG. 15 is a circuit diagram showing the structure of the transfer control circuit 11a and FIG. 16 is a timing chart illustrating the operation of the transfer control circuit 11a.
As shown in FIG. 15, the transfer control circuit 11a includes NAND gates G1, G2 and G5, inverters G3 and G4 and a buffer G6.
The operation will be described in a case where a data transmission path in a subsequent stage is in a ready state.
When the data transmission path in the subsequent stage is in a ready state, an "H" (logic high level) transmission acknowledging signal AK2 is applied from a transfer control circuit in the subsequent stage. In response to a fall of a transmission signal C1 applied from a preceding stage portion to "L" (logic low level), the output of the NAND gate G2 attains "H". As a result, a transmission acknowledging signal AK1 output from the inverter G4 attains "L" (inhibited state). Meanwhile, the output of the NAND gate G5 attains "L" and the output of the inverter G3 attains "H". At this time, with the transmission acknowledging signal AK2 attaining "H", the output of the NAND gate G1 falls to "L". As a result, a transmission signal C2 falls to "L".
The data hold circuit 12a shown in FIG. 14 holds the input data DI and outputs the same as the output data DO in response to the fall of the transmission signal C2.
The transfer control circuit in the subsequent stage receiving the transmission signal C2 brings the transmission acknowledging signal AK2 to "L" in response to the fall of the transmission signal C2.
In response to the fall of the output of the NAND gate G1, the output of the NAND gate G5 attains an "H" and the inverter G3 attains "L" to bring the output of the NAND gate G1 to "H" again. As a result, the transmission signal C2 rises to "H" again. The transmission signal C2 falls to "L" and rises to "H" after a lapse of a predetermined time in this way.
The transmission signal C1 applied from the preceding stage portion rises to "H" after a lapse of a fixed time. The output of the NAND gate G2 falls to "L" and the output of the inverter G4 rises to "H". As a result, the transmission acknowledging signal AK1 again attains "H" (acknowledged state).
As described in the foregoing, when the transmission acknowledging signal AK2 applied from the transfer control circuit in the subsequent stage is at "H" (acknowledged state), the transmission acknowledging signal AK1 to be applied to the preceding stage attains "L" (inhibited state) in response to a fall of the transmission signal C1 applied from the preceding stage portion and after a lapse of a fixed time, the transmission signal C2 to be applied to the transfer control circuit in the subsequent stage falls to "L".
An operation in the event that a data transmission path in the subsequent stage is clogged will be described.
In this case, the transmission acknowledging signal AK2 applied from the transfer control circuit in the subsequent state is at "L" (inhibited state). When the transmission signal C1 applied from the preceding stage portion falls to "L", the output of the NAND gate G2 attains "H" and the output of the inverter G4 falls to "L". As a result, transmission acknowledging signal AK1 falls to "L". When the transmission acknowledging signal AK2 applied from the transfer control circuit in the subsequent stage is at "L" (inhibited state), the output of the NAND G1 is at "H". Therefore, as long as the transmission acknowledging signal AK2 is at "L", the transmission signal C2 to be applied to the transfer control circuit in the subsequent stage maintains "H". No data is transmitted from the data transmission path 10a to a data transmission path in the subsequent stage as a result.
When the transmission acknowledging signal AK2 applied from the transfer control circuit in the subsequent stage rises to "H" (acknowledged state), the output of the NAND gate G1 falls to a "L" level. As a result, the transmission signal C2 to be applied to the transfer control circuit in the subsequent stage falls to "L". In response to the fall of the transmission signal C2, the data hold circuit 12a shown in FIG. 14 holds the input data DI and outputs the same as the output data DO.
Meanwhile, in response to the fall of the transmission signal C2 applied from the transfer control circuit 11a, the transfer control circuit in the subsequent stage brings the transmission acknowledging signal AK2 to "L" (inhibited state) after a lapse of a fixed time. In response to the rise of the transmission acknowledging signal AK2 applied from the transfer control circuit in the subsequent stage, the transmission acknowledging signal AK1 to be applied to the preceding stage portion rises to "H" (acknowledged state) after a lapse of a fixed time.
As described above, when the transmission acknowledging signal AK2 applied from the transfer control circuit in the subsequent stage is at "L" (inhibited state), the transmission signal C2 to be applied to the transfer control circuit in the subsequent stage does not fall to "L". In other words, when the data transmission path in the subsequent stage is clogged, data transmission from the data transmission path 10a to the data transmission path in the subsequent stage is held off for the transmission acknowledging signal AK2 attaining "H" (acknowledged state).
In the above-described conventional data transmission apparatus, data is autonomously and sequentially transmitted to data transmission paths in the following stages in turn when a data transmission path in a subsequent stage is empty. It is therefore difficult to trace operations step by step while advancing the data stage by stage. It is also difficult to test an operation margin of the transfer control, an operation margin of the logic arranged between the data transmission paths and the like.
A data transmission apparatus using a simple shift register operable in synchronization with an externally applied clock signal without a handshaking circuit, does not perform such control as holding off data transfer when a subsequent stage is clogged and transferring data when the subsequent stage is empty.